Not Applicable.
Not Applicable.
The present embodiments relate to electronic circuits and are more particularly directed to an extended drain metal oxide semiconductor (xe2x80x9cMOSxe2x80x9d) transistor having a configuration for enhanced electrostatic discharge (xe2x80x9cESDxe2x80x9d) protection.
Semiconductor devices have become prevalent in all aspects of electronic circuits, and the design of such devices often involves a choice from various circuit elements such as one or more of different transistor devices. For example, drain extended MOS (xe2x80x9cDEMOSxe2x80x9d) transistors are used in various circuits, where one instance is a circuit that has different operating voltages. Such a circuit may include two different operating voltages, where a first voltage is used at the input/output (xe2x80x9cI/Oxe2x80x9d) level while a second and lower voltage is used for the operational core of the circuit. In these cases, transistors suitable for use at the higher I/O voltages are required, and one type of such a transistor is the DEMOS transistor. DEMOS transistors also may be used in applications where the voltage on the drain exceeds the normal voltage rating of the gate oxide.
While DEMOS transistors have found beneficial use in certain circuit implementations, another aspect of device design is device reliability. For example, one common cause of concern to the reliability of a circuit is potential damage from ESD. ESD occurs due to a relatively short period of relatively high voltage or current imposed on the device. For example, ESD can be caused by the human body, by poorly grounded machinery such as test equipment, or in electrically noisy environments as may be incurred in automotive applications or in consumer applications, including computers. In any event, due to the risk of ESD, devices are often engineered and tested to ensure that they can withstand certain levels of ESD. In this regard, the present inventor has determined that while DEMOS transistors may prove useful such as described above and particularly for use at the I/O level of a circuit, a standard DEMOS configuration may be unreliable for certain levels of ESD, as further detailed later.
By way of further background, U.S. Pat. No. 5,627,394 (xe2x80x9cthe ""394 Patentxe2x80x9d), is entitled LD-MOS transistor, and issued May 6, 1997. The ""394 Patent describes an LD (lateral diffusion) transistor designed to increase device breakdown strength. The transistor includes a highly-doped source region separated from a highly-doped drain region, but further includes a very lightly doped extended drain region in contact with the highly-doped drain region. Of note, the very lightly doped extended drain region is formed by implanting dopants at a level between 3.0xc3x971012 to 5.0xc3x971012/cm2. The present inventor expects that such a light doping causes the lightly doped extended drain region to completely deplete when the transistor is in its off state, thereby rendering that region in effect an insulator during that time, whereas, when the device is on the light doping level will conduct, but will provide a considerable resistance thereby limiting current flow through the transistor. Additionally, the ""394 Patent notes that the use of this structure eliminates the need for an n-well to be formed below the highly-doped drain region.
In view of the above, there arises a need to improve upon the prior art as is achieved by the preferred embodiments described below.
In the preferred embodiment, there is a semiconductor device comprising a first transistor and a second transistor, both formed in a semiconductor substrate. The first transistor comprises a gate conductor and a gate insulator separating the gate conductor from a semiconductor material and defining a channel area in the semiconductor material opposite from the gate conductor. The first transistor further comprises a source comprising a first doped region of a first conductivity type and adjacent the channel area. Further, the first transistor comprises a drain. The drain comprises a first well adjacent the channel area and having a first concentration of the first conductivity type and a first doped region portion and a second doped portion. The first doped portion has a second concentration of the first conductivity type. The second concentration is greater than the first concentration and the first doped region portion has a common interface with the first well. The second doped region portion has the second concentration of the first conductivity type, wherein the second doped region portion has no common interface with the first well and is not adjacent the channel area. The second transistor comprises a second well formed using a same implant step as the first well and thereby having the first concentration of the first conductivity type. The second transistor further comprises a first source/drain and a second source/drain, both comprising a second conductivity type complementary of the first conductivity type and formed within the second well. Other attributes are also disclosed and claimed.